The disclosure relates generally to semiconductor devices and more specifically to stacked nanosheet transistors.
Gate-all-around (GAA) stacked nanosheet structures, such as GAA stacked nanosheet MOSFETs, are candidates for advanced technology nodes. GAA stacked nanosheet structures offer good electrostatic control, thereby enabling CMOS device scaling. Furthermore, GAA stacked nanosheet MOSFETs offer increased current drive per foot print. However, work function (WF) control as well as achieving multi threshold voltages (Vth) in stacked nanosheets are challenging due to the asymmetry of the structure, especially for the top sheet which is semi-confined compared to the bottom sheets.
Therefore, it would be desirable to have a method and apparatus that take into account at least some of the issues discussed above, as well as other possible issues.